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| MCP3550/1/3 Low-Power, Single-Channel 22-Bit Delta-Sigma ADCs Features * 22-bit ADC in Small 8-pin MSOP Package with Automatic Internal Offset and Gain Calibration * Low-Output Noise of 2.5 VRMS with Effective Resolution of 21.9 bits (MCP3550/1) * 3 V Typical Offset Error * 2 ppm Typical Full Scale Error * 6 ppm Maximum INL Error * Total Unadjusted Error Less Than 10 ppm * No Digital Filter Settling Time, Single-Command Conversions through 3-wire SPI Interface * Ultra-Low Conversion Current (MCP3550/1): - 100 A typical (VDD = 2.7V) - 120 A typical (VDD = 5.0V) * Differential Input with VSS to VDD Common Mode Range * 2.7V to 5.5V Single-Supply Operation * Extended Temperature Range: - -40C to +125C Description The Microchip Technology Inc. MCP3550/1/3 devices are 2.7V to 5.5V low-power, 22-bit Delta-Sigma Analog-to-Digital Converters (ADCs). The devices offer output noise as low as 2.5 VRMS, with a total unadjusted error of 10 ppm. The family exhibits 6 ppm Integral Non-Linearity (INL) error, 3 V offset error and less than 2 ppm full scale error. The MCP3550/1/3 devices provide high accuracy and low noise performance for applications where sensor measurements (such as pressure, temperature and humidity) are performed. With the internal oscillator and high oversampling rate, minimal external components are required for high-accuracy applications. This product line has fully differential analog inputs, making it compatible with a wide variety of sensor, industrial control or process control applications. The MCP3550/1/3 devices operate from -40C to +125C and are available in the space-saving 8-pin MSOP and SOIC packages. Applications * * * * * * Weigh Scales Direct Temperature Measurement 6-digit DVMs Instrumentation Data Acquisition Strain Gauge Measurement Package Types: MCP3550/1/3 MSOP, SOIC VREF 1 VIN+ 2 VIN- 3 VSS 4 VSS VDD 8 VDD 7 CS 6 SDO/RDY 5 SCK Block Diagram VREF VIN- Internal Oscillator (c) 2009 Microchip Technology Inc. SINC 4 VIN+ Serial Interface 3rd-Order DS ADC Modulator w/ Internal Calibration SCK SDO RDY CS VDD POR DS21950E-page 1 MCP3550/1/3 NOTES: DS21950E-page 2 (c) 2009 Microchip Technology Inc. MCP3550/1/3 1.0 1.1 ELECTRICAL CHARACTERISTICS Maximum Ratings* VDD...................................................................................7.0V All inputs and outputs w.r.t VSS .... .......... -0.3V to VDD+ 0.3V Difference Input Voltage ....................................... |VDD - VSS| Output Short Circuit Current ................................ Continuous Current at Input Pins ....................................................2 mA Current at Output and Supply Pins ............................10 mA Storage Temperature ....................................-65C to +150C Ambient temp. with power applied ................-55C to +125C ESD protection on all pins (HBM, MM) ............ 6 kV, 400V Maximum Junction Temperature (TJ). .........................+150C Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at -40C TA +85C, VDD = 2.7V or 5.0V. VREF = 2.5V. VIN+ = VIN- = VCM = VREF/2. All ppm units use 2*VREF as full scale range. Unless otherwise noted, specification applies to entire MCP3550/1/3 family. Parameters Noise Performance (MCP3550/1) No Missing Codes Output Noise Effective Resolution Noise Performance (MCP3553) No Missing Codes Output Noise Effective Resolution Conversion Times MCP3550-50 MCP3550-60 MCP3551 MCP3553 Accuracy Integral Non-Linearity Offset Error INL VOS -- -12 -- -- Positive Full Scale Error Negative Full Scale Error Offset Drift Positive/Negative Full Scale Error Drift Note 1: 2: 3: 4: 5: 6: VFS,P VFS,N -10 -10 -- -- 2 3 4 6 2 2 0.040 0.028 6 +12 -- -- +10 +10 -- -- ppm V V V ppm ppm ppm/C ppm/C TA = +25C only (Note 2) TA = +25C TA = +85C TA = +125C TA = +25C only TA = +25C only tCONV tCONV tCONV tCONV -2.0% -2.0% -2.0% -2.0% 80 66.67 73.1 16.67 +2.0% +2.0% +2.0% +2.0% ms ms ms ms NMC eN ER 20 -- -- -- 6 20.6 -- -- -- bits VRMS bits RMS VREF = 5V At DC (Note 5) NMC eN ER 22 -- -- -- 2.5 21.9 -- -- -- bits VRMS bits RMS VREF = 5V At DC (Note 5) Sym Min Typ Max Units Conditions This parameter is established by characterization and not 100% tested. INL is the difference between the endpoints line and the measured code at the center of the quantization band. This current is due to the leakage current and the current due to the offset voltage between VIN+ and VIN-. Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. VREF = 5V. Characterized by design, but not tested. Rejection performance depends on internal oscillator accuracy; see Section 4.0 "Device Overview" for more information on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61 Hz. (c) 2009 Microchip Technology Inc. DS21950E-page 3 MCP3550/1/3 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at -40C TA +85C, VDD = 2.7V or 5.0V. VREF = 2.5V. VIN+ = VIN- = VCM = VREF/2. All ppm units use 2*VREF as full scale range. Unless otherwise noted, specification applies to entire MCP3550/1/3 family. Parameters Rejection Performance (1,6) Sym Min -- -- Typ -135 -115 -135 -85 -120 Max -- -- -- -- -- Units dB dB dB dB dB Conditions VCM range from 0 to VDD VCM varies from 0V to VDD MCP3551 only, VDD varies from 4.5V to 5.5V MCP3550-50 or MCP3550-60 only at 50 or 60 Hz respectively, VDD varies from 4.5V to 5.5V MCP3551 only, 0 < VCM < VDD, -VREF < VIN = (VIN + -VIN-) < +VREF MCP3550-50 or MCP3550-60 only at 50 or 60 Hz respectively, 0 < VCM < VDD, -VREF < VIN = (VIN + -VIN-) < +VREF Common Mode DC Rejection Power Supply DC Rejection Common Mode 50/60 Hz Rejection Power Supply 50/60 Hz Rejection Power Supply 50/60 Hz Rejection CMRR PSRR PSRR -- -- -- Normal Mode 50 and 60 Hz Rejection Normal Mode 50 or 60 Hz Rejection NMRR -- -85 -- dB NMRR -- -120 -- dB Analog Inputs Differential Input Range Absolute/Common Mode Voltages Analog Input Sampling Capacitor Differential Input Impedance Shutdown Mode Leakage Current Reference Input Voltage Range Reference Input Sampling Capacitor Reference Input Impedance Shutdown Mode Reference Leakage Current Power Requirements Power Supply Voltage Range MCP3550-50, MCP3551 Supply Current MCP3550-60, MCP3553 Supply Current Supply Current, Sleep Mode Supply Current, Shutdown Mode Serial Interface Voltage Input High (CS, SCK) Voltage Input Low (CS, SCK) Voltage Output High (SDO/RDY) Note 1: 2: 3: 4: 5: 6: VIH VIL VOH 0.7 VDD -- VDD - 0.5 -- -- -- -- 0.4 -- V V V VOH = 1 mA, VDD = 5.0V VDD IDD IDD IDDSL IDDS 2.7 -- -- -- -- -- -- -- 120 100 140 120 10 -- 1 5.5 170 -- 185 -- V A A A A A A CS = SCK = VDD VDD = 5V VDD = 2.7V VDD = 5V VDD = 2.7V 0.1 -- -- -- -- 15 2.4 1 VDD -- -- -- V pF M nA Note 5 Note 4 VIN+ = VIN- = VSS; CS = VDD VIN+ - VIN-VREF VSS - 0.3 -- -- -- -- -- 10 2.4 1 +VREF VDD + 0.3 -- -- -- V V pF M nA VIN+ = VIN- = VDD; CS = VDD (Note 3) Note 5 This parameter is established by characterization and not 100% tested. INL is the difference between the endpoints line and the measured code at the center of the quantization band. This current is due to the leakage current and the current due to the offset voltage between VIN+ and VIN-. Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. VREF = 5V. Characterized by design, but not tested. Rejection performance depends on internal oscillator accuracy; see Section 4.0 "Device Overview" for more information on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61 Hz. DS21950E-page 4 (c) 2009 Microchip Technology Inc. MCP3550/1/3 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at -40C TA +85C, VDD = 2.7V or 5.0V. VREF = 2.5V. VIN+ = VIN- = VCM = VREF/2. All ppm units use 2*VREF as full scale range. Unless otherwise noted, specification applies to entire MCP3550/1/3 family. Parameters Voltage Output Low (SDO/RDY) Input leakage Current (CS, SCK) Internal Pin Capacitance (CS, SCK, SDO/RDY) Note 1: 2: 3: 4: 5: 6: Sym VOL ILI CINT Min -- -1 -- Typ -- -- 5 Max 0.4 1 -- Units V A pF Note 1 Conditions VOH = -1 mA, VDD = 5.0V This parameter is established by characterization and not 100% tested. INL is the difference between the endpoints line and the measured code at the center of the quantization band. This current is due to the leakage current and the current due to the offset voltage between VIN+ and VIN-. Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. VREF = 5V. Characterized by design, but not tested. Rejection performance depends on internal oscillator accuracy; see Section 4.0 "Device Overview" for more information on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61 Hz. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Thermal Package Resistances Thermal Resistance, 8L-MSOP Thermal Resistance, 8L-SOIC JA JA -- -- 211 149.5 -- -- C/W C/W TA TA -40 -40 -- -- +85 +125 C C Sym Min Typ Max Units Conditions SERIAL TIMINGS Electrical Specifications: Unless otherwise indicated, all parameters apply at -40C TA +85C, VDD = 3.3V or 5.0V, SDO load = 50 pF. Parameters CLK Frequency CLK High CLK Low CLK fall to output data valid CS low to indicate RDY state CS minimum low time RDY flag setup time CS rise to output disable CS disable time Power-up to CS LOW CS High to Shutdown Mode Sym fSCK tHI tLO tDO tRDY tCSL tSU tDIS tCSD tPUCSL tCSHSD Min -- 90 90 0 0 50 20 20 90 -- -- Typ -- -- -- -- -- -- -- -- -- 10 10 Max 5 -- -- 90 50 -- -- -- -- -- -- Units MHz ns ns ns ns ns ns ns ns s s Conditions (c) 2009 Microchip Technology Inc. DS21950E-page 5 MCP3550/1/3 tRDY tCSD CS tCSL tDIS tCSHSD SDO /RDY tDO tSU tHI fSCK tLO SCK FIGURE 1-1: Serial Timing. VDD CS tPUCSL FIGURE 1-2: Power-up Timing. DS21950E-page 6 (c) 2009 Microchip Technology Inc. MCP3550/1/3 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise specified, TA = +25C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-. All ppm units use 2*VREF as full scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family. 5 4 3 2 1 0 -1 -2 -3 -4 -5 -2.5 10 +125 C INL Error (ppm) 1.5 2.5 +85 C 8 6 4 2 0 INL (ppm) -40 C +25 C -1.5 -0.5 VIN (V) 0.5 0 0.5 1 1.5 2 2.5 VREF (V) 3 3.5 4 4.5 5 FIGURE 2-1: (VDD = 2.7V). 5 4 3 2 1 0 -1 -2 -3 -4 -5 -2.5 INL Error vs. Input Voltage FIGURE 2-4: VREF. 10 9 8 7 6 5 4 3 2 1 0 -50 -25 0 Maximum INL Error vs. +125 C +85 C - 40 C +25 C -1.5 -0.5 VIN (V) 0.5 1.5 2.5 Max INL (ppm) INL (ppm) 25 50 75 100 125 Temperature (C) FIGURE 2-2: (VDD = 5.0V). 10 8 6 4 2 0 -2 -4 -6 -8 -10 -5 -4 -3 INL Error vs. Input Voltage FIGURE 2-5: Temperature. 10 9 8 7 6 5 4 3 2 1 0 -2.5 Maximum INL Error vs. +125 C +85 C Output Noise (VRMS) INL (ppm) MCP3553 +25 C -40 C MCP3550/1 -2 -1 0 VIN (V) 1 2 3 4 5 -1.5 -0.5 0.5 VIN (Volts) 1.5 2.5 FIGURE 2-3: INL Error vs. Input Voltage (VDD = 5.0V, VREF = 5V). FIGURE 2-6: Output Noise vs. Input Voltage (VDD = 2.7V). (c) 2009 Microchip Technology Inc. DS21950E-page 7 MCP3550/1/3 Note: Unless otherwise specified, TA = +25C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-. All ppm units use 2*VREF as full scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family. 15 Output Noise (V RMS) Output Noise (VRMS ) 10 9 8 7 6 5 4 3 2 1 0 -50 -25 0 10 MCP3553 MCP3553 5 MCP3550/1 MCP3550/1 0 -2.5 -1.5 -0.5 0.5 1.5 2.5 VIN (V) 25 50 75 Temperature (C) 100 125 FIGURE 2-7: Output Noise vs. Input Voltage (VDD = 5.0V). u FIGURE 2-10: Temperature. 5 4 Output Noise vs. 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0.0 1.0 Output Noise (VRMS) MCP3553 Offset (V) 5.0 3 2 1 0 MCP3550/1 2.0 3.0 4.0 2.5 3 3.5 4 VDD (V) 4.5 5 5.5 VREF (V) FIGURE 2-8: Output Noise vs. VREF . FIGURE 2-11: (VCM = 0V). 7 6 Offset Error vs VDD 10 9 8 7 6 5 4 3 2 1 0 2.5 3 3.5 Output Noise (V RMS) MCP3553 Offset (V) 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 MCP3550/1 4 VDD (V) 4.5 5 5.5 Temperature (C) FIGURE 2-9: Output Noise vs.VDD. FIGURE 2-12: Offset Error vs. Temperature (VREF = 5.0V). DS21950E-page 8 (c) 2009 Microchip Technology Inc. MCP3550/1/3 Note: Unless otherwise specified, TA = +25C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-. All ppm units are ratioed against 2*VREF . Unless otherwise noted, graphs apply to entire MCP3550/1/3 family. 5 4 3 2 1 0 -1 -2 -3 -4 -5 2.5 3 4000 Number of Occurrences 3500 3000 2500 2000 1500 1000 500 0 -15 -10 -5 0 5 10 15 Full Scale Error (ppm) Positive Full Scale VDD = 5V VREF = 2.5V VCM = 1.25V VIN = 0V TA = 25C 16384 consecutiv e readings Negative Full Scale 3.5 4 VDD (V) 4.5 5 5.5 Output Code (LSB) FIGURE 2-13: Full Scale Error vs. VDD . FIGURE 2-16: Histogram. 1800 Number of Occurrences 1600 1400 1200 1000 800 600 400 200 0 -15 -10 MCP3550/1 Output Noise 10 8 6 4 2 0 -2 -4 -6 -8 -10 -50 -25 Full Scale Error (ppm) Positive Full Scale VDD = 5V VREF = 2.5V VCM = 1.25V VIN = 0V TA = 25C 16384 consecutive readings Negative Full Scale 0 25 50 75 100 125 Temperature (C) -5 0 5 Output Code (LSB) 10 15 FIGURE 2-14: Temperature. 10 8 6 4 2 0 -2 -4 -6 -8 -10 -50 Full Scale Error vs. FIGURE 2-17: Histogram. MCP3553 Output Noise Negative Full Scale -25 0 25 50 75 100 125 Temperature (C) TUE (ppm) Positive Full Scale 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 -2.0 -3.0 -4.0 -5.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 VIN (V) FIGURE 2-15: Full Scale Error vs. Temperature (VREF = 5.0V). Full Scale Error (ppm) FIGURE 2-18: Total Unadjusted Error (TUE) vs. Input Voltage (VDD = 2.7V). (c) 2009 Microchip Technology Inc. DS21950E-page 9 MCP3550/1/3 Note: Unless otherwise specified, TA = +25C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-. All ppm units use 2*VREF as full scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family. 5 4 3 2 1 0 -1 -2 -3 -4 -5 -2.5 6 Maximum TUE (ppm) 5 4 3 2 1 0 -2 -1.5 -1 -0.5 0 0.5 VIN (V) 1 1.5 2 2.5 -50 -25 0 25 50 75 100 125 Temperature (C) TUE (ppm) FIGURE 2-19: Total Unadjusted Error (TUE) vs. Input Voltage. 10 8 6 4 2 0 -2 -4 -6 -8 -10 -5 -4 -3 -2 -1 0 VIN (V) 1 2 3 4 5 FIGURE 2-22: Temperature. 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 2.5 2.7 Maximum TUE vs. TUE (ppm) TUE (ppm) 3 3.3 VDD (V) 4 5 5.5 FIGURE 2-20: Total Unadjusted Error (TUE) vs. Input Voltage (VREF = 5.0V). 10 9 8 7 6 5 4 3 2 1 0 0 1 2 VREF (V) 3 4 5 FIGURE 2-23: Maximum TUE vs. VDD. 0.6 0.5 0.4 IDDS (A) 0.3 0.2 0.1 0 -0.1 -50 -25 0 25 50 75 100 125 Temperature (C) MCP3553 MCP3550/1 Maximum TUE (ppm) FIGURE 2-21: Maximum TUE vs. VREF . FIGURE 2-24: IDDS vs. Temperature. DS21950E-page 10 (c) 2009 Microchip Technology Inc. MCP3550/1/3 Note: Unless otherwise specified, TA = +25C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-. All ppm units use 2*VREF as full scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family. 200 180 160 140 120 100 80 60 40 20 0 2.5 160 140 MCP3550-60, MCP3553 MCP3550-50, MCP3550/1 MCP3550-60, MCP3553 MCP3550-50, MCP3550/1 120 IDD (A) 5.5 100 80 60 40 20 0 IDD (A) 3 3.5 4 VDD (V) 4.5 5 -50 -25 0 25 50 75 100 125 Temperature (C) FIGURE 2-25: IDD vs. VDD. FIGURE 2-26: IDD vs. Temperature. (c) 2009 Microchip Technology Inc. DS21950E-page 11 MCP3550/1/3 NOTES: DS21950E-page 12 (c) 2009 Microchip Technology Inc. MCP3550/1/3 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: MCP3550/1/3 MSOP, SOIC 1 2 3 4 5 6 7 8 PIN FUNCTION TABLE Symbol VREF VIN+ VINVSS SCK SDO/RDY CS VDD I/O/P I I I P I O I P Description Reference Voltage Analog Input Pin Non-inverting Analog Input Pin Inverting Analog Input Pin Ground Pin Serial Clock Digital Input Pin Data/Ready Digital Output Pin Chip Select Digital Input Pin Positive Supply Voltage Pin Type Identification: I = Input; O = Output; P = Power 3.1 Voltage Reference (VREF) 3.3 Supply Voltage (VDD, VSS) The MCP3550/1/3 devices accept single-ended reference voltages from 0.1V to VDD. Since the converter output noise is dominated by thermal noise, which is independent of the reference voltage, the output noise is not significantly improved by diminishing the reference voltage at the VREF input pin. A reduced voltage reference will significantly improve the INL performance (see Figure 2-4); the INL max error is proportional to VREF2. VDD is the power supply pin for the analog and digital circuitry within the MCP3550/1/3. This pin requires an appropriate bypass capacitor of 0.1 F. The voltage on this pin should be maintained in the 2.7V to 5.5V range for specified operation. VSS is the ground pin and the current return path for both analog and digital circuitry of the MCP3550/1/3. If an analog ground plane is available, it is recommended that this device be tied to the analog ground plane of the Printed Circuit Board (PCB). 3.2 Analog Inputs (VIN+, VIN-) The MCP3550/1/3 devices accept a fully differential analog input voltage to be connected on the VIN+ and VIN- input pins. The differential voltage that is converted is defined by VIN = VIN+ - VIN-. The differential voltage range specified for ensured accuracy is from -VREF to +VREF. However, the converter will still output valid and usable codes with the inputs overranged by up to 12% (see Section 5.0 "Serial Interface") at room temperature. This overrange is clearly specified by two overload bits in the output code. The absolute voltage range on these input pins extends from VSS - 0.3V to VDD + 0.3V. Any voltage above or below this range will create leakage currents through the Electrostatic Discharge (ESD) diodes. This current will increase exponentially, degrading the accuracy and noise performance of the device. The common mode of the analog inputs should be chosen such that both the differential analog input range and the absolute voltage range on each pin are within the specified operating range defined in Section 1.0 "Electrical Characteristics". 3.4 Serial Clock (SCK) SCK synchronizes data communication with the device. The device operates in both SPI mode 1,1 and SPI mode 0,0. Data is shifted out of the device on the falling edge of SCK. Data is latched in on the rising edge of SCK. During CS high times, the SCK pin can idle either high or low. 3.5 Data Output (SDO/RDY) SDO/RDY is the output data pin for the device. Once a conversion is complete, this pin will go active-low, acting as a ready flag. Subsequent falling clock edges will then place the 24-bit data word (two overflow bits and 22 bits of data, see Section 5.0 "Serial Interface") on the SPI bus through the SDO pin. Data is clocked out on the falling edge of SCK. (c) 2009 Microchip Technology Inc. DS21950E-page 13 MCP3550/1/3 3.6 Chip Select (CS) CS gates all communication to the device and can be used to select multiple devices that share the same SCK and SDO/RDY pins. This pin is also used to control the internal conversions, which begin on the falling edge of CS. Raising CS before the first internal conversion is complete places the device in Single Conversion mode. Leaving CS low will place the device in Continuous Conversion mode (i.e., additional internal conversions will automatically occur). CS may be tied permanently low for two-wire Continuous Conversion mode operation. SDO/RDY enters a highimpedance state with CS high. DS21950E-page 14 (c) 2009 Microchip Technology Inc. MCP3550/1/3 4.0 DEVICE OVERVIEW The MCP3550/1/3 devices are 22-bit delta-sigma ADCs that include fully differential analog inputs, a third-order delta-sigma modulator, a fourth-order modified SINC decimation filter, an on-chip, low-noise internal oscillator, a power supply monitoring circuit and an SPI 3-wire digital interface. These devices can be easily used to measure low-frequency, low-level signals such as those found in pressure transducers, temperature, strain gauge, industrial control or process control applications. The power supply range for this product family is 2.7V to 5.5V; the temperature range is -40C to +125C. The functional block diagram for the MCP3550/1/3 devices is shown in Figure 4-1. A Power-On Reset (POR) monitoring circuit is included to ensure proper power supply voltages during the conversion process. The clock source for the part is internally generated to 0.5% over the full-power supply voltage range and industrial temperature range. This stable clock source allows for superior conversion repeatability and minimal drift across conversions. The MCP3550/1/3 devices employ a delta-sigma conversion technique to realize up to 22 bits of no missing code performance with 21.9 Effective Number of Bits (ENOB). These devices provide single-cycle conversions with no digital filter settling time. Every conversion includes an internal offset and gain autocalibration to reduce device error. These calibrations are transparent to the user and are done in real-time during the conversion. Therefore, these devices do not require any additional time or conversion to proceed, allowing easy usage of the devices for multiplexed applications. The MCP3550/1/3 devices incorporate a fourth-order digital decimation filter in order to allow superior averaging performance, as well as excellent line frequency rejection capabilities. The oversampling frequency also reduces any external anti-aliasing filter requirements. The MCP3550/1/3 devices communicate with a simple 3-wire SPI interface. The interface controls the conversion start event, with an added feature of an auto-conversion at system power-up by tying the CS pin to logic-low. The device can communicate with bus speeds of up to 5 MHz, with 50 pF capacitive loading. The interface offers two conversion modes: Single Conversion mode for multiplexed applications and a Continuous Conversion mode for multiple conversions in series. Every conversion is independent of each other. That is, all internal registers are flushed between conversions. When the device is not converting, it automatically goes into Shutdown mode and, while in this mode, consumes less than 1 A. Reference Input Differential Analog Input Gain and Offset Calibration Charge Transfer Third-Order Modulator Clock Bit Stream Digital Decimation Filter (SINC4) Conversion Code SPI 3-wire Interface Output Code Internal Oscillator FIGURE 4-1: MCP3550/1/3 Functional Block Diagram. (c) 2009 Microchip Technology Inc. DS21950E-page 15 MCP3550/1/3 4.1 MCP3550/1/3 Delta-Sigma Modulator with Internal Offset and Gain Calibration 4.2 Digital Filter The MCP3550/1/3 devices include a digital decimation filter, which is a fourth-order modified SINC filter. This filter averages the incoming bit stream from the modulator and outputs a 22-bit conversion word in binary two's complement. When all bits have been processed by the filter, the output code is ready for SPI communication, the RDY flag is set on the SDO/RDY pin and all the internal registers are reset in order to process the next conversion. Like the commonly used SINC filter, the modified SINC filter in the MCP3550/1/3 family has the main notch frequency located at fS/(OSR*L), where fS is the bit stream sample frequency. OSR is the Oversampling Ratio and L is the order of the filter. The MCP3550-50 device has the main filter notch located at 50 Hz. For the MCP3550-60 device, the notch is located at 60 Hz. The MCP3551 device has its notch located at 55 Hz, and for the MCP3553 device, the main notch is located at 240 Hz, with an OSR of 128. (see Table 4-1 for rejection performance). The digital decimation SINC filter has been modified in order to offer staggered zeros in its transfer function. This modification is intended to widen the main notch in order to be less sensitive to oscillator deviation or linefrequency drift. The MCP3551 filter has staggered zeros spread in order to reject both 50 Hz and 60 Hz line frequencies simultaneously (see Figure 4-2). The converter core of the MCP3550/1/3 devices is a third-order delta-sigma modulator with automatic gain and offset error calibrations. The modulator uses a 1-bit DAC structure. The delta-sigma modulator processes the sampled charges through switched capacitor structures controlled by a very low drift oscillator for reduced clock jitter. During the conversion process, the modulator outputs a bit stream with the bit frequency equivalent to the fOSC/4 (see Table 4-1). The high oversampling implemented in the modulator ensures very high resolution and high averaging factor to achieve lownoise specifications. The bit stream output of the modulator is then processed by the digital decimation filter in order to provide a 22-bit output code at a data rate of 12.5 Hz for the MCP3550-50, 15 Hz for the MCP3550-60, 13.75 Hz for the MCP3551 and 60 Hz for the MCP3553. Since the oversampling ratio is lower with the MCP3553 device, a much higher output data rate is achieved while still achieving 20 bits No Missing Codes (NMC) and 20.6 ENOB. A self-calibration of offset and gain occurs at the onset of every conversion. The conversion data available at the output of the device is always calibrated for offset and gain through this process. This offset and gain auto-calibration is performed internally and has no impact on the speed of the converter since the offset and gain errors are calibrated in real-time during the conversion. The real-time offset and gain calibration schemes do not affect the conversion process. TABLE 4-1: Device MCP3550-50 MCP3550-60 MCP3551 DATA RATE, OUTPUT NOISE AND DIGITAL FILTER SPECIFICATIONS BY DEVICE Output Data Rate (tCONV) (Note) 80.00 ms 66.67 ms 72.73 ms Output Noise (VRMS) 2.5 2.5 2.5 Primary Notch (Hz) 50 60 55 Sample Frequency (fS) 25600 Hz 30720 Hz 28160 Hz Internal Clock fOSC 102.4 kHz 122.88 kHz 112.64 kHz 50/60 Hz Rejection -120 dB min. at 50 Hz -120 dB min. at 60 Hz -82 dB min. from 48 Hz to 63 Hz. 82 dB at 50 Hz and -88 dB at 60 Hz Not Applicable MCP3553 Note: 16.67 ms 6 240 30720 Hz 122.88 kHz For the first conversion after exiting Shutdown, tCONV must include an additional 144 fOSC periods before the conversion is complete and the RDY (Ready) flag appears on SDO/RDY. DS21950E-page 16 (c) 2009 Microchip Technology Inc. MCP3550/1/3 : 0 Normal Mode Rejection (dB) 0 -20 -40 -60 -80 -100 -120 -20 Attenuation (dB) -40 -60 -80 -100 -120 0 50 100 Frequency (Hz) 150 200 -140 0 28160 56320 84480 112640 140800 168960 197120 225280 253440 Frequency (Hz) FIGURE 4-2: SINC Filter Response, MCP3550-50 Device. : FIGURE 4-5: SINC Filter Response at Integer Multiples of the Sampling Frequency (fs). 0 -20 Attenuation (dB) -40 -60 -80 -100 -120 0 60 120 Frequency (Hz) 180 240 4.3 Internal Oscillator The MCP3550/1/3 devices include a highly stable and accurate internal oscillator that provides clock signals to the delta-sigma ADC with minimum jitter. The oscillator is a specialized structure with a low temperature coefficient across the full range of specified operation. See Table 4-1 for oscillator frequencies. The conversion time is an integer multiple of the internal clock period and, therefore, has the same accuracy as the internal clock frequency. The internal oscillator frequency is 102.4 kHz 1% for the MCP3550-50, 112.64 kHz 1% for the MCP3551, and 122.88 kHz 1% for the MCP3550-60 and MCP3553 devices, across the full power supply voltage and specified temperature ranges. The notch of the digital filter is proportional to the internal oscillator frequency, with the exact notch frequency equivalent to the oscillator accuracy (< 1% deviation). This high accuracy, combined with wide notches, will ensure that the MCP3551 will have simultaneous 50 Hz and 60 Hz line frequency rejection and the MCP3550-50 or MCP3550-60 devices will have greater than 120 dB rejection (at either 50 or 60 Hz) by the digital filtering, even when jitter is present. The internal oscillator is held in the reset condition when the part is in Shutdown mode to ensure very low power consumption (< 1 A in Shutdown mode). The internal oscillator is independent of all serial digital interface edges (i.e., state machine processing the digital SPI interface is asynchronous with respect to the internal clock edges). FIGURE 4-3: SINC Filter Response, MCP3550-60 Device. : 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 50 60 70 80 90 100 110 Frequency (Hz) FIGURE 4-4: SINC Filter Response, MCP3551 Device, Simultaneous 50/60 Hz Rejection. (c) 2009 Microchip Technology Inc. Attenuation (dB) DS21950E-page 17 MCP3550/1/3 4.4 Differential Analog Inputs 4.5 Voltage Reference Input Pin The MCP3550/1/3 devices accept a fully differential analog input voltage to be connected to the VIN+ and VIN- input pins. The differential voltage that is converted is defined by VIN = VIN+ - VIN-. The differential voltage range specified for ensured accuracy is from -VREF to +VREF. The converter will output valid and usable codes from -112% to 112% of output range (see Section 5.0 "Serial Interface") at room temperature. The 12% overrange is clearly specified by two overload bits in the output code: OVH and OVL. This feature allows for system calibration of a positive gain error. The absolute voltage range on these input pins extends from VSS - 0.3V to VDD + 0.3V. If the input voltages are above or below this range, the leakage currents of the ESD diodes will increase exponentially, degrading the accuracy and noise performance of the converter. The common mode of the analog inputs should be chosen such that both the differential analog input range and absolute voltage range on each pin are within the specified operating range defined in Section 1.0 "Electrical Characteristics". Both the analog differential inputs and the reference input have switched-capacitor input structures. The input capacitors are charged and discharged alternatively with the input and the reference in order to process a conversion. The charge and discharge of the input capacitors create dynamic input currents at the VIN+ and VIN- input pins inversely proportional to the sampling capacitor. This current is a function of the differential input voltages and their respective common modes. The typical value of the differential input impedance is 2.4 M, with VCM = 2.5V, VDD = VREF = 5V. The DC leakage current caused by the ESD input diodes, even though on the order of 1 nA, can cause additional offset errors proportional to the source resistance at the VIN+ and VIN- input pins. From a transient response standpoint and as a firstorder approximation, these input structures form a simple RC filtering circuit with the source impedance in series with the RON (switched resistance when closed) of the input switch and the sampling capacitor. In order to ensure the accuracy of the sampled charge, proper settling time of the input circuit has to be considered. Slow settling of the input circuit will create additional gain error. As a rule of thumb, in order to obtain 1 ppm absolute measurement accuracy, the sampling period must be 14 times greater than the input circuit RC time constant. The MCP3550/1/3 devices accept a single-ended external reference voltage, to be connected on the VREF input pin. Internally, the reference voltage for the ADC is a differential voltage with the non-inverting input connected to the VREF pin and the inverting input connected to the VSS pin. The value of the reference voltage is VREF - VSS and the common mode of the reference is always (VREF - VSS)/2. The MCP3550/1/3 devices accept a single-ended reference voltage from 0.1V to VDD. The converter output noise is dominated by thermal noise that is independent of the reference voltage. Therefore, the output noise is not significantly improved by lowering the reference voltage at the VREF input pin. However, a reduced reference voltage will significantly improve the INL performance since the INL max error is proportional to VREF2 (see Figure 2-4). The charge and discharge of the input capacitor create dynamic input currents at the VREF input pin inversely proportional to the sampling capacitor, which is a function of the input reference voltage. The typical value of the single-ended input impedance is 2.4 M, with VDD = VREF = 5V. The DC leakage current caused by the ESD input diodes, though on the order of 1 nA typically, can cause additional gain error proportional to the source resistance at the VREF pin. 4.6 Power-On Reset (POR) The MCP3550/1/3 devices contain an internal PowerOn Reset (POR) circuit that monitors power supply voltage VDD during operation. This circuit ensures correct device start-up at system power-up and powerdown events. The POR has built-in hysteresis and a timer to give a high degree of immunity to potential ripple and noise on the power supplies, as well as to allow proper settling of the power supply during powerup. A 0.1 F decoupling capacitor should be mounted as close as possible to the VDD pin, providing additional transient immunity. The threshold voltage is set at 2.2V, with a tolerance of approximately 5%. If the supply voltage falls below this threshold, the MCP3550/1/3 devices will be held in a reset condition or in Shutdown mode. When the part is in Shutdown mode, the power consumption is less than 1 A. The typical hysteresis value is around 200 mV in order to prevent reset during brown-out or other glitches on the power supply. DS21950E-page 18 (c) 2009 Microchip Technology Inc. MCP3550/1/3 Once a power-up event has occurred, the device must require additional time before a conversion can take place. During this time, all internal analog circuitry must settle before the first conversion can occur. An internal timer counts 32 internal clock periods before the internal oscillator can provide clock to the conversion process. This allows all internal analog circuitry to settle to their proper operating point. This timing is typically less than 300 s, which is negligible compared to one conversion time (e.g. 72.7 ms for the MCP3551). Figure 4-6 illustrates the conditions for a power-up and power-down event under typical start-up conditions. VDD 4.8 Sleep Mode During Sleep mode, the device is not converting and is awaiting data retrieval; the internal analog circuitry is still running and the device typically consumes 10 A. In order to restart a conversion while in Sleep mode, toggling CS to a logic-high (placing the part in Shutdown mode) and then back to a logic-low will restart the conversion. Sleep can only be entered in Single Conversion mode. Once a conversion is complete in Single Conversion mode, the device automatically enters Sleep mode. 2.2V 2.0V 300 s 0V Reset Start-up Normal Operation Reset Time FIGURE 4-6: Power-On Reset Operation. 4.7 Shutdown Mode When not internally converting, the two modes of operation for the MCP3550/1/3 devices are the Shutdown and Sleep modes. During Shutdown mode, all internal analog circuitry, including the POR, is turned off and the device consumes less than 1 A. When exiting Shutdown mode, the device must require additional time before a conversion can take place. During this time, all internal analog circuitry must settle before the first conversion can occur. An internal timer counts 32 internal clock periods before the internal oscillator can provide clock to the conversion process. This allows all internal analog circuitry to settle to their proper operating point. This timing is typically less than 300 s, which is negligible compared to one conversion time (72.7 ms for MCP3551). (c) 2009 Microchip Technology Inc. DS21950E-page 19 MCP3550/1/3 NOTES: DS21950E-page 20 (c) 2009 Microchip Technology Inc. MCP3550/1/3 5.0 5.1 SERIAL INTERFACE Overview Serial communication between the microcontroller and the MCP3550/1/3 devices is achieved using CS, SCK and SDO/RDY. There are two modes of operation: Single Conversion and Continuous Conversion. CS controls the conversion start. There are 24 bits in the data word: 22 bits of conversion data and two overflow bits. The conversion process takes place via the internal oscillator and the status of this conversion must be detected. The typical method of communication is shown in Figure 5-1. The status of the internal conversion is the SDO/RDY pin and is available with CS low. A High state on SDO/RDY means the device is busy converting, while a Low state means the conversion is finished and data is ready for transfer using SCK. SDO/RDY remains in a high-impedance state when CS is held high. CS must be low when clocking out the data using SCK and SDO/RDY. Bit 22 is Overflow High (OVH) when VIN > VREF - 1 LSB, OVH toggles to logic `1', detecting an overflow high in the analog input voltage. Bit 23 is Overflow Low (OVL) when VIN < -VREF, OVL toggles to logic `1', detecting an overflow low in the analog input voltage. The state OVH = OVL = `1' is not defined and should be considered as an interrupt for the SPI interface meaning erroneous communication. Bit 21 to bit 0 represents the output code in 22-bit binary two's complement. Bit 21 is the sign bit and is logic `0' when the differential analog input is positive and logic `1' when the differential analog input is negative. From Bit 20 to bit 0, the output code is given MSb first (MSb is bit 20 and LSB is Bit 0). When the analog input value is comprised between -VREF and VREF - 1 LSB, the two overflow bits are set to logic `0'. The relationship between input voltage and output code is shown in Figure 5-1. The delta-sigma modulator saturation point for the differential analog input is located at around 112% of VREF (at room temperature), meaning that the modulator will still give accurate output codes with an overrange of 12% below or above the reference voltage. Unlike the usual 22-bit device, the 22-bit output code will not lock at 0x1FFFFF for positive sign inputs or 0x200000 for negative sign inputs in order to take advantage of the overrange capabilities of the device. This can be practical for closed-loop operations, for instance. In case of an overflow, the output code becomes a 23-bit two's complement output code, where the sign bit will be the OVL bit. If an overflow high or low is detected, OVL (bit 23) becomes the sign bit (instead of bit 21), the MSb is then bit 21 and the converter can be used as a 23-bit two's complement code converter, with output code from bits B21 to B0, and OVL as the sign bit. Figure 5-1 summarizes the output coding data format with or without overflow high and low. CS SCK SDO/RDY READY D R OO 21 20 19 18 17 LH 16 15 14 13 12 11 10 9 8 76543 21 0 HI-Z FIGURE 5-1: Typical Serial Device Communication and Example Digital Output Codes for Specific Analog Input Voltages. (c) 2009 Microchip Technology Inc. DS21950E-page 21 MCP3550/1/3 5.2 Controlling Internal Conversions and the Internal Oscillator In Continuous Conversion mode, a consecutive conversion will be automatic. In this mode, the device is continuously converting, independent of the serial interface. The most recent conversion data will always be available in the Output register. When the device exits Shutdown, there is an internal power-up delay that must be observed. During Shutdown mode, on the falling edge of CS, the conversion process begins. During this process, the internal oscillator clocks the delta-sigma modulator and the SINC filter until a conversion is complete. This conversion time is tCONV and the timing is shown in Figure 5-2. At the end of tCONV, the digital filter has settled completely and there is no latency involved with the digital SINC filter of the MCP3550/1/3. The two modes of conversion for the MCP3550/1/3 devices are Single Conversion and Continuous Conversion. In Single Conversion mode, a consecutive conversion will not automatically begin. Instead, after a single conversion is complete and the SINC filter have settled, the device puts the data into the output register and enters shutdown. CS Int. Osc tCONV Sleep Shutdown SCK (opt) x24 SDO/RDY Hi-Z Hi-Z FIGURE 5-2: Single Conversion Mode. CS Int. Osc tCONV tCONV tCONV Shutdown SCK (opt) x24 SDO/RDY Hi-Z FIGURE 5-3: Continuous Conversion Mode. DS21950E-page 22 (c) 2009 Microchip Technology Inc. MCP3550/1/3 5.3 Single Conversion Mode 5.4 Continuous Conversion Mode If a rising edge of Chip Select (CS) occurs during tCONV, a subsequent conversion will not take place and the device will enter low-power Shutdown mode after tCONV completes. This is referred to as Single Conversion mode. This operation is demonstrated in Figure 5-2. Note that a falling edge of CS during the same conversion that detected a rising edge, as in Figure 5-2, will not initiate a new conversion. The data must be read during sleep mode, with CSN low, and will be lost as soon as the part enters in shutdown mode (with a rising edge of CSN). After the final data bit has been clocked out on the 25th clock, the SDO/RDY pin will go active-high. If no rising edge of CS occurs during any given conversion per Figure 5-3, a subsequent conversion will take place and the contents of the previous conversion will be overwritten. This operation is demonstrated in Figure 5-5. Once conversion output data has started to be clocked out, the output buffer is not refreshed until all 24 bits have been clocked. A complete read must occur in order to read the next conversion in this mode. The subsequent conversion data to be read will then be the most recent conversion. The conversion time is fixed and cannot be shortened by the rising edge of CS. This rising edge will place the part in Shutdown mode and all conversion data will be lost. The transfer of data from the SINC filter to the output buffer is demonstrated in Figure 5-5. If the previous conversion data is not clocked out of the device, it will be lost and replaced by the new conversion. When the device is in Continuous Conversion mode, the most recent conversion data is always present at the output register for data retrieval. CS Int. Osc tCONV 5.3.1 READY FUNCTION OF SDO/RDY PIN, SINGLE CONVERSION MODE At every falling edge of CS during the internal conversion, the state of the internal conversion is latched on the SDO/RDY pin to give ready or busy information. A High state means the device is currently performing an internal conversion and data cannot be clocked out. A Low state means the device has finished its conversion and the data is ready for retrieval on the falling edge of SCK. This operation is demonstrated in Figure 5-4. Note that the device has been put into Single Conversion mode with the first rising edge of CS. Note: The Ready state is latched on each falling edge of CS and will not dynamically update if CS is held low. CS must be toggled high through low. A tCONV B tCONV C SCK & SDO/RDY Conversion B data is clocked out of the device here. CS Int. Osc tCONV FIGURE 5-5: Most Current Continuous Conversion Mode Data. If a conversion is in process, it cannot be terminated with the rising edge of CS. SDO/RDY must first transition to a Low state, which will indicate the end of conversion. SDO/RDY Hi-Z FIGURE 5-4: RDY Functionality in Single Conversion Mode. (c) 2009 Microchip Technology Inc. DS21950E-page 23 MCP3550/1/3 5.4.1 READY FUNCTION OF SDO/RDY PIN IN CONTINUOUS CONVERSION MODE 5.4.2 2-WIRE CONTINUOUS CONVERSION OPERATION, (CS TIED PERMANENTLY LOW) The device enters Continuous Conversion mode if no rising edge of CS is seen during tCONV and consecutive conversions ensue. SDO/RDY will be high, indicating that a conversion is in process. When a conversion is complete, SDO/RDY will change to a Low state. With the Low state of SDO/RDY after this first conversion, the conversion data can be accessed with the combination of SCK and SDO/RDY. If the data ready event happens during the clocking out of the data, the data ready bit will be displayed after the complete 24-bit word communication (i.e., the data ready event will not interrupt a data transfer). If 24 bits of data are required from this conversion, they must be accessed during this communication. You can terminate data transition by bringing CS high, but the remaining data will be lost and the converter will go into Shutdown mode. Once the data has been transmitted by the converter, the SDO/RDY pin will remain in the LSB state until the 25th falling edge of SCK. At this point, SDO/RDY is released from the Data Acquisition mode and changed to the RDY state. Note: The RDY state is not latched to CS in this mode; the RDY flag dynamically updates on the SDO/RDY pin and remains in this state until data is clocked out using the SCK pin. It is possible to use only two wires to communicate with the MCP3550/1/3 devices. In this state, the device is always in Continuous Conversion mode, with internal conversions continuously occurring. This mode can be entered by having CS low during power-up or changing it to a low position after power-up. If CS is low at powerup, the first conversion of the converter is initiated approximately 300 s after the power supply has stabilized. DS21950E-page 24 (c) 2009 Microchip Technology Inc. MCP3550/1/3 5.5 Using The MCP3550/1/3 with Microcontroller (MCU) SPI Ports In SPI mode 1,1, data is read using only 24 clocks or three byte transfers. The data ready bit must be read by testing the SDO/RDY line prior to a falling edge of the clock. In SPI mode 0,0, data is read using 25 clocks or four byte transfers. Please note that the data ready bit is included in the transfer as the first bit in this mode. It is required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Figure 5-6 depicts the operation shown in SPI mode 1,1, which requires that the SCK from the MCU idles in the High state, while Figure 5-7 shows the similar case of SPI Mode 0,0, where the clock idles in the Low state. The waveforms in the figures are examples of an MCU operating the SPI port in 8-bit mode, and the MCP3550/1/3 devices do not require data in 8-bit groups. CS SCK SDO/RDY D R OO 21 20 19 18 17 HL 16 15 14 13 12 11 10 9 8 7654321 0 MCU Receive Buffer OL OH 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data stored into MCU receive register after transmission of first byte Data stored into MCU receive register after transmission of second byte Data stored into MCU receive register after transmission of third byte FIGURE 5-6: CS SCK SPI Communication - Mode 1,1. SDO/RDY DR OO 21 20 19 18 17 HL 16 15 14 13 12 11 10 9 8 7654321 0 MCU Receive Buffer DR OH OL 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data stored into MCU receive register after transmission of first byte Data stored into MCU receive register after transmission of second byte Data stored into MCU receive register after transmission of third byte Data stored into MCU receive register after transmission of fourth byte FIGURE 5-7: SPI Communication - Mode 0,0. (c) 2009 Microchip Technology Inc. DS21950E-page 25 MCP3550/1/3 NOTES: DS21950E-page 26 (c) 2009 Microchip Technology Inc. MCP3550/1/3 6.0 6.1 PACKAGING INFORMATION Package Marking Information 8-Lead MSOP XXXXXX YWWNNN Example: 3553E 951256 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example (MCP3550): 3550-50E e3 SN^^ 0951 256 Example (MCP3551): MCP3551E e3 SN^^ 0951 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2009 Microchip Technology Inc. DS21950E-page 27 MCP3550/1/3 /HDG 3ODVWLF 0LFUR 6PDOO 2XWOLQH 3DFNDJH 06 >0623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 b A A2 c e A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV 1 H $ $ $ ( ( ' / / I F L1 0,//,0(7(56 0,1 120 %6& %6& %6& %6& 5() 0$; L /HDG :LGWK E 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % DS21950E-page 28 (c) 2009 Microchip Technology Inc. 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DS21950E-page 29 MCP3550/1/3 /HDG 3ODVWLF 6PDOO 2XWOLQH 61 1DUURZ 1RWH PP %RG\ >62,&@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS21950E-page 30 (c) 2009 Microchip Technology Inc. MCP3550/1/3 APPENDIX A: REVISION HISTORY Revision E (April 2009) The following is the list of modifications: 1. 2. Numerous changes made throughout document. Too numerous to itemize. DC Characteristics Table, Conversion Times: Changed all minimums from -1.0% to -2.0%. Changed typical for MCP3551 from 72.73 to 73.1. Changed all maximums from +1.0% to +2.0%. Packaging Outline drawings updated.. 3. Revision D (January 2007) The following is the list of modifications: * This update includes revisions to the packaging diagrams. Revision C (December 2005) The following is the list of modifications: * Added MCP3550-50, MCP3550-60 references throughout this document. Revision B (October 2005) The following is the list of modifications: * Changed LSb refefences to LSB. Revision A (September 2005) * Original Release of this Document. (c) 2009 Microchip Technology Inc. DS21950E-page 31 MCP3550/1/3 NOTES: DS21950E-page 32 (c) 2009 Microchip Technology Inc. MCP3550/1/3 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X Temperature Range /XX Package Examples: a) b) Extended Temp., 8LD MSOP. MCP3550T-50E/MS: Tape and Reel, Extended Temp., 8LD MSOP. MCP3550-60E/SN: Extended Temp., 8LD SOIC. MCP3550T-60E/SN: Tape and Reel, Extended Temp., 8LD SOIC. MCP3551-E/MS: MCP3551T-E/MS: Extended Temp., 8LD MSOP. Tape and Reel, Extended Temp., 8LD MSOP. Extended Temp., 8LD SOIC. Tape and Reel, Extended Temp., 8LD SOIC. MCP3550-50E/MS: Device: MCP3550-50: Single Channel 22-Bit Delta-Sigma ADC MCP3550T-50: Single Channel 22-Bit Delta-Sigma ADC (Tape and Reel) MCP3550-60: Single Channel 22-Bit Delta-Sigma ADC MCP3550T-60: Single Channel 22-Bit Delta-Sigma ADC (Tape and Reel) MCP3551: Single Channel 22-Bit Delta-Sigma ADC MCP3551T: Single Channel 22-Bit Delta-Sigma ADC (Tape and Reel) MCP3553: Single Channel 22-Bit Delta-Sigma ADC MCP3553T: Single Channel 22-Bit Delta-Sigma ADC (Tape and Reel) = -40C to +125C c) d) a) b) Temperature Range: E Package: a) b) MCP3553-E/SN: MCP3553T-E/SN: MS = Plastic MSOP, 8-lead SN = Plastic SOIC (150 mil Body), 8-lead (c) 2009 Microchip Technology Inc. DS21950E-page 33 MCP3550/1/3 NOTES: DS21950E-page 34 (c) 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2009 Microchip Technology Inc. DS21950E-page 35 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 03/26/09 DS21950E-page 36 (c) 2009 Microchip Technology Inc. |
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